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at91_smc.h File Reference


Detailed Description

AT91 static memory controller.

 *
 * $Log: at91_smc.h,v $
 * Revision 1.1  2006/08/31 19:10:38  haraldkipp
 * New peripheral register definitions for the AT91SAM9260.
 *
 *
 * 


SMC Setup Register

#define SMC_SETUP(cs)   (SMC_BASE + 0x10 * cs + 0x00)
 SMC setup register address.
#define SMC_NWE_SETUP   0x0000003F
 NWE setup length mask.
#define SMC_NWE_SETUP_LSB   0
 NWE setup length LSB.
#define SMC_NCS_WR_SETUP   0x00003F00
 NCS setup length in write access mask.
#define SMC_NCS_WR_SETUP_LSB   8
 NCS setup length in write access LSB.
#define SMC_NRD_SETUP   0x003F0000
 NRD setup length mask.
#define SMC_NRD_SETUP_LSB   16
 NRD setup length LSB.
#define SMC_NCS_RD_SETUP   0x3F000000
 NCS setup length in read access mask.
#define SMC_NCS_RD_SETUP_LSB   24
 NCS setup length in read access LSB.

SMC Pulse Register

#define SMC_PULSE(cs)   (SMC_BASE + 0x10 * cs + 0x04)
 SMC pulse register address.
#define SMC_NWE_PULSE   0x0000003F
 NWE pulse length mask.
#define SMC_NWE_PULSE_LSB   0
 NWE pulse length LSB.
#define SMC_NCS_WR_PULSE   0x00003F00
 NCS pulse length in write access mask.
#define SMC_NCS_WR_PULSE_LSB   8
 NCS pulse length in write access LSB.
#define SMC_NRD_PULSE   0x003F0000
 NRD pulse length mask.
#define SMC_NRD_PULSE_LSB   16
 NRD pulse length LSB.
#define SMC_NCS_RD_PULSE   0x3F000000
 NCS pulse length in read access mask.
#define SMC_NCS_RD_PULSE_LSB   24
 NCS pulse length in read access LSB.

SMC Cycle Register

#define SMC_CYCLE(cs)   (SMC_BASE + 0x10 * cs + 0x08)
 SMC cycle register address.
#define SMC_NWE_CYCLE   0x000001FF
 Total write cycle length mask.
#define SMC_NWE_CYCLE_LSB   0
 Total write cycle length LSB.
#define SMC_NRD_CYCLE   0x01FF0000
 Total read cycle length mask.
#define SMC_NRD_CYCLE_LSB   16
 Total read cycle length LSB.

SMC Mode Register

#define SMC_MODE(cs)   (SMC_BASE + 0x10 * cs + 0x0C)
 SMC mode register address.
#define SMC_READ_MODE   0x00000001
 Read operation mode.
#define SMC_WRITE_MODE   0x00000002
 Write operation mode.
#define SMC_EXNW_MODE   0x00000030
 NWAIT mode mask.
#define SMC_EXNW_MODE_DISABLED   0x00000000
 NWAIT mode mask.
#define SMC_EXNW_MODE_FROZEN   0x00000020
 NWAIT mode mask.
#define SMC_EXNW_MODE_READY   0x00000030
 NWAIT mode mask.
#define SMC_BAT   0x00000100
 Byte access mode.
#define SMC_DBW   0x00003000
 Data bus width.
#define SMC_DBW_8   0x00000000
 8-bit data bus
#define SMC_DBW_16   0x00001000
 16-bit data bus
#define SMC_DBW_32   0x00002000
 32-bit data bus
#define SMC_TDF_CYCLES   0x000F0000
 Data float time mask.
#define SMC_TDF_CYCLES_LSB   0x000F0000
 Data float time LSB.
#define SMC_TDF_MODE   0x00100000
 TDF optimization.
#define SMC_PMEN   0x01000000
 Page mode enable.
#define SMC_PS   0x30000000
 Page size mask.
#define SMC_PS_4   0x30000000
 4-byte page
#define SMC_PS_8   0x30000000
 8-byte page
#define SMC_PS_16   0x30000000
 16-byte page
#define SMC_PS_32   0x30000000
 32-byte page


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