Including this file is deprecated. Use cfg/arch/avr.h.
Defines | |
| #define | RTL_RESET_PORT PORTE |
| #define | RTL_RESET_DDR DDRE |
| #define | RTL_RESET_BIT 4 |
| RTL8019AS hardware reset input. | |
| #define | RTL_SIGNAL_PORT PORTE |
| #define | RTL_SIGNAL_PIN PINE |
| #define | RTL_SIGNAL_DDR DDRE |
| #define | RTL_SIGNAL sig_INTERRUPT5 |
| Interrupt signal handler of RTL_SIGNAL_BIT. | |
| #define | RTL_SIGNAL_BIT 5 |
| Interrupt signal bit for Ethernut 1.x Ethernet controller. | |
| #define | NIC_BASE 0xC000 |
| Ethernut 2.x Ethernet controller base address. | |
| #define | LAN_SIGNAL_PORT PORTE |
| #define | LAN_SIGNAL_PIN PINE |
| #define | LAN_SIGNAL_DDR DDRE |
| #define | LAN_SIGNAL sig_INTERRUPT5 |
| Interrupt signal handler of LAN_SIGNAL_BIT. | |
| #define | LAN_SIGNAL_BIT 5 |
| Interrupt signal bit for Ethernut 2.x Ethernet controller. | |