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Medianut Hardware.
[Hardware Layout.]

Ports used by the Medianut MP3 Add-On. More...

Defines
#define	VS_SCK_PORT
#define	VS_SCK_DDR
#define	VS_SCK_BIT
	VS1001 serial control interface clock input bit.
#define	VS_SS_PORT
#define	VS_SS_DDR
#define	VS_SS_BIT
	VS1001 serial data interface clock input bit.
#define	VS_SI_PORT
#define	VS_SI_DDR
#define	VS_SI_BIT
	VS1001 serial control interface data input.
#define	VS_SO_PIN
#define	VS_SO_DDR
#define	VS_SO_BIT
	VS1001 serial control interface data output.
#define	VS_XCS_PORT
#define	VS_XCS_DDR
#define	VS_XCS_BIT
	VS1001 active low chip select input.
#define	VS_BSYNC_PORT
#define	VS_BSYNC_DDR
#define	VS_BSYNC_BIT
	VS1001 serial data interface bit sync.
#define	VS_RESET_PORT
#define	VS_RESET_DDR
#define	VS_RESET_BIT
	VS1001 hardware reset input.
#define	VS_DREQ_PORT
#define	VS_DREQ_PIN
#define	VS_DREQ_DDR
#define	VS_DREQ_BIT
	VS1001 data request output.
#define	LCD_DATA_PORT
#define	LCD_DATA_DDR
#define	LCD_DATA_BITS
	LCD data lines, either upper or lower 4 bits.
#define	LCD_ENABLE_PORT
#define	LCD_ENABLE_DDR
#define	LCD_ENABLE_BIT
	LCD enable output.
#define	LCD_REGSEL_PORT
#define	LCD_REGSEL_DDR
#define	LCD_REGSEL_BIT
	LCD register select output.
#define	LCD_LIGHT_PORT
#define	LCD_LIGHT_DDR
#define	LCD_LIGHT_BIT
	LCD output to switch backlight.
#define	IR_SIGNAL_PORT
#define	IR_SIGNAL_PIN
#define	IR_SIGNAL_DDR
#define	IR_SIGNAL_BIT
	Infrared decoder signal bit.

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Detailed Description

Ports used by the Medianut MP3 Add-On.

Medianut is an add-on board and can be attached to the Ethernut expansion port. It contains a VS1001K MP3 decoder, a LCD interface and an infrared receiver.

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Define Documentation

#define IR_SIGNAL_DDR

Data direction register of IR_SIGNAL_BIT .

#define IR_SIGNAL_PIN

Port input register of IR_SIGNAL_BIT .

#define IR_SIGNAL_PORT

Port output register of IR_SIGNAL_BIT .

#define LCD_DATA_DDR

Data direction register of LCD_DATA_BITS .

#define LCD_DATA_PORT

Port output register of LCD_DATA_BITS .

#define LCD_ENABLE_DDR

Data direction register of LCD_ENABLE_BIT .

#define LCD_ENABLE_PORT

Port output register of LCD_ENABLE_BIT .

#define LCD_LIGHT_DDR

Data direction register of LCD_LIGHT_BIT .

#define LCD_LIGHT_PORT

Port output register of LCD_LIGHT_BIT .

#define LCD_REGSEL_DDR

Data direction register of LCD_REGSEL_BIT .

#define LCD_REGSEL_PORT

Port output register of LCD_REGSEL_BIT .

#define VS_BSYNC_BIT

VS1001 serial data interface bit sync. The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte.

#define VS_BSYNC_DDR

Data direction register of VS_BSYNC_BIT .

#define VS_BSYNC_PORT

Port output register of VS_BSYNC_BIT .

#define VS_DREQ_DDR

Data direction register of VS_DREQ_BIT .

#define VS_DREQ_PIN

Port input register of VS_DREQ_BIT .

#define VS_DREQ_PORT

Port output register of VS_DREQ_BIT .

#define VS_RESET_DDR

Data direction register of VS_RESET_BIT .

#define VS_RESET_PORT

Port output register of VS_RESET_BIT .

#define VS_SCK_BIT

VS1001 serial control interface clock input bit. The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder.

#define VS_SCK_DDR

Data direction register of VS_SCK_BIT .

#define VS_SCK_PORT

Port register of VS_SCK_BIT .

#define VS_SI_BIT

VS1001 serial control interface data input. The decoder samples this input on the rising edge of SCK if XCS is low.

#define VS_SI_DDR

Data direction register of VS_SI_BIT .

#define VS_SI_PORT

Port output register of VS_SI_BIT .

#define VS_SO_BIT

VS1001 serial control interface data output. If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state.

#define VS_SO_DDR

Data direction register of VS_SO_BIT .

#define VS_SO_PIN

Port input register of VS_SO_BIT .

#define VS_SS_DDR

Data direction register of VS_SS_BIT .

#define VS_SS_PORT

Port output register of VS_SS_BIT .

#define VS_XCS_BIT

VS1001 active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state.

#define VS_XCS_DDR

Data direction register of VS_XCS_BIT .

#define VS_XCS_PORT

Port output register of VS_XCS_BIT .

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