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LAN91C111 registers
[LAN91C111 device driver]

SMSC LAN91C111 register definitions. More...

Data Structures
struct	_NICINFO
	Network interface controller information structure. More...
struct	_NICINFO
	Network interface controller information structure. More...
Defines
#define	NIC_BSR
	Bank select register.
#define	NIC_TCR
	Bank 0 - Transmit control register.
#define	TCR_SWFDUP
#define	TCR_EPH_LOOP
#define	TCR_STP_SQET
#define	TCR_FDUPLX
#define	TCR_MON_CSN
#define	TCR_NOCRC
#define	TCR_PAD_EN
#define	TCR_FORCOL
#define	TCR_LOOP
#define	TCR_TXENA
#define	NIC_EPHSR
	Bank 0 - EPH status register.
#define	NIC_RCR
	Bank 0 - Receive control register.
#define	RCR_SOFT_RST
#define	RCR_FILT_CAR
#define	RCR_ABORT_ENB
#define	RCR_STRIP_CRC
#define	RCR_RXEN
#define	RCR_ALMUL
#define	RCR_PRMS
#define	RCR_RX_ABORT
#define	NIC_ECR
	Bank 0 - Counter register.
#define	NIC_MIR
	Bank 0 - Memory information register.
#define	NIC_RPCR
	Bank 0 - Receive / PHY control register.
#define	RPCR_SPEED
#define	RPCR_DPLX
#define	RPCR_ANEG
#define	RPCR_LEDA_PAT
#define	RPCR_LEDB_PAT
#define	NIC_CR
	Bank 1 - Configuration register.
#define	CR_EPH_EN
#define	NIC_BAR
	Bank 1 - Base address register.
#define	NIC_IAR
	Bank 1 - Individual address register.
#define	NIC_GPR
	Bank 1 - General purpose register.
#define	NIC_CTR
	Bank 1 - Control register.
#define	CTR_RCV_BAD
#define	CTR_AUTO_RELEASE
#define	NIC_MMUCR
	Bank 2 - MMU command register.
#define	NIC_PNR
	Bank 2 - Packet number register.
#define	NIC_ARR
	Bank 2 - Allocation result register.
#define	NIC_FIFO
	Bank 2 - FIFO ports register.
#define	NIC_PTR
	Bank 2 - Pointer register.
#define	NIC_DATA
	Bank 2 - Data register.
#define	NIC_IST
	Bank 2 - Interrupt status register.
#define	NIC_ACK
	Bank 2 - Interrupt acknowledge register.
#define	NIC_MSK
	Bank 2 - Interrupt mask register.
#define	INT_MD
#define	INT_ERCV
#define	INT_EPH
#define	INT_RX_OVRN
#define	INT_ALLOC
#define	INT_TX_EMPTY
#define	INT_TX
#define	INT_RCV
#define	NIC_MT
	Bank 3 - Multicast table register.
#define	NIC_MGMT
	Bank 3 - Management interface register.
#define	MGMT_MDOE
#define	MGMT_MCLK
#define	MGMT_MDI
#define	MGMT_MDO
#define	NIC_REV
	Bank 3 - Revision register.
#define	NIC_ERCV
	Bank 3 - Early RCV register.
#define	NIC_PHYCR
	PHY control register.
#define	PHYCR_RST
#define	PHYCR_LPBK
#define	PHYCR_SPEED
#define	PHYCR_ANEG_EN
#define	PHYCR_PDN
#define	PHYCR_MII_DIS
#define	PHYCR_ANEG_RST
#define	PHYCR_DPLX
#define	PHYCR_COLST
#define	NIC_PHYSR
	PHY status register.
#define	PHYSR_CAP_T4
#define	PHYSR_CAP_TXF
#define	PHYSR_CAP_TXH
#define	PHYSR_CAP_TF
#define	PHYSR_CAP_TH
#define	PHYSR_CAP_SUPR
#define	PHYSR_ANEG_ACK
#define	PHYSR_REM_FLT
#define	PHYSR_CAP_ANEG
#define	PHYSR_LINK
#define	PHYSR_JAB
#define	PHYSR_EXREG
#define	NIC_PHYID1
	PHY identifier register 1.
#define	NIC_PHYID2
	PHY identifier register 1.
#define	NIC_PHYANAD
	PHY auto-negotiation advertisement register.
#define	PHYANAD_NP
#define	PHYANAD_ACK
#define	PHYANAD_RF
#define	PHYANAD_T4
#define	PHYANAD_TX_FDX
#define	PHYANAD_TX_HDX
#define	PHYANAD_10FDX
#define	PHYANAD_10_HDX
#define	PHYANAD_CSMA
#define	NIC_PHYANRC
	PHY auto-negotiation remote end capability register.
#define	NIC_PHYCFR1
	PHY configuration register 1.
#define	NIC_PHYCFR2
	PHY configuration register 2.
#define	NIC_PHYSOR
	PHY status output register.
#define	PHYSOR_INT
#define	PHYSOR_LNKFAIL
#define	PHYSOR_LOSSSYNC
#define	PHYSOR_CWRD
#define	PHYSOR_SSD
#define	PHYSOR_ESD
#define	PHYSOR_RPOL
#define	PHYSOR_JAB
#define	PHYSOR_SPDDET
#define	PHYSOR_DPLXDET
#define	NIC_PHYMSK
	PHY mask register.
#define	PHYMSK_MINT
#define	PHYMSK_MLNKFAIL
#define	PHYMSK_MLOSSSYN
#define	PHYMSK_MCWRD
#define	PHYMSK_MSSD
#define	PHYMSK_MESD
#define	PHYMSK_MRPOL
#define	PHYMSK_MJAB
#define	PHYMSK_MSPDDT
#define	PHYMSK_MDPLDT
Typedefs
typedef _NICINFO	NICINFO
	Network interface controller information type.

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Detailed Description

SMSC LAN91C111 register definitions.

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Define Documentation

#define CR_EPH_EN

NIC_CR bit mask, .

#define CTR_AUTO_RELEASE

NIC_CTR bit mask, transmit packets automatically released.

#define CTR_RCV_BAD

NIC_CTR bit mask.

#define INT_ALLOC

allocation interrupt bit mask.

#define INT_EPH

protocol interrupt bit mask.

#define INT_ERCV

receive interrupt bit mask.

#define INT_MD

state change interrupt bit mask.

#define INT_RCV

interrupt bit mask.

#define INT_RX_OVRN

overrun interrupt bit mask.

#define INT_TX

complete interrupt bit mask.

#define INT_TX_EMPTY

empty interrupt bit mask.

#define MGMT_MCLK

NIC_MGMT bit mask, drives MDCLK pin.

#define MGMT_MDI

NIC_MGMT bit mask, reflects MDI pin status.

#define MGMT_MDO

NIC_MGMT bit mask, drives MDO pin.

#define MGMT_MDOE

NIC_MGMT bit mask, enables MDO pin.

#define NIC_ACK

Bank 2 - Interrupt acknowledge register.

#define NIC_ARR

Bank 2 - Allocation result register. This byte register is updated upon a command.

#define NIC_BAR

Bank 1 - Base address register.

#define NIC_BSR

Bank select register.

#define NIC_CR

Bank 1 - Configuration register.

#define NIC_CTR

Bank 1 - Control register.

#define NIC_DATA

Bank 2 - Data register.

#define NIC_ECR

Bank 0 - Counter register.

#define NIC_EPHSR

Bank 0 - EPH status register.

#define NIC_ERCV

Bank 3 - Early RCV register.

#define NIC_FIFO

Bank 2 - FIFO ports register.

#define NIC_GPR

Bank 1 - General purpose register.

#define NIC_IAR

Bank 1 - Individual address register.

#define NIC_IST

Bank 2 - Interrupt status register.

#define NIC_MGMT

Bank 3 - Management interface register.

#define NIC_MIR

Bank 0 - Memory information register.

#define NIC_MMUCR

Bank 2 - MMU command register.

#define NIC_MSK

Bank 2 - Interrupt mask register.

#define NIC_MT

Bank 3 - Multicast table register.

#define NIC_PHYANAD

PHY auto-negotiation advertisement register.

#define NIC_PHYANRC

PHY auto-negotiation remote end capability register.

#define NIC_PHYCFR1

PHY configuration register 1.

#define NIC_PHYCFR2

PHY configuration register 2.

#define NIC_PHYCR

PHY control register.

#define NIC_PHYID1

PHY identifier register 1.

#define NIC_PHYID2

PHY identifier register 1.

#define NIC_PHYMSK

PHY mask register.

#define NIC_PHYSOR

PHY status output register.

#define NIC_PHYSR

PHY status register.

#define NIC_PNR

Bank 2 - Packet number register. This byte register specifies the accessible transmit packet number.

#define NIC_PTR

Bank 2 - Pointer register.

#define NIC_RCR

Bank 0 - Receive control register.

#define NIC_REV

Bank 3 - Revision register.

#define NIC_RPCR

Bank 0 - Receive / PHY control register.

#define NIC_TCR

Bank 0 - Transmit control register.

#define PHYANAD_10_HDX

NIC_PHYANAD bit mask, indicates 10BASE-T half duplex capability.

#define PHYANAD_10FDX

NIC_PHYANAD bit mask, indicates 10BASE-T full duplex capability.

#define PHYANAD_ACK

NIC_PHYANAD bit mask, acknowledged.

#define PHYANAD_CSMA

NIC_PHYANAD bit mask, indicates 802.3 CSMA capability.

#define PHYANAD_NP

NIC_PHYANAD bit mask, exchanging next page information.

#define PHYANAD_RF

NIC_PHYANAD bit mask, remote fault.

#define PHYANAD_T4

NIC_PHYANAD bit mask, indicates 100BASE-T4 capability.

#define PHYANAD_TX_FDX

NIC_PHYANAD bit mask, indicates 100BASE-TX full duplex capability.

#define PHYANAD_TX_HDX

NIC_PHYANAD bit mask, indicates 100BASE-TX half duplex capability.

#define PHYCR_ANEG_EN

NIC_PHYCR bit mask, .

#define PHYCR_ANEG_RST

NIC_PHYCR bit mask, .

#define PHYCR_COLST

NIC_PHYCR bit mask, .

#define PHYCR_DPLX

NIC_PHYCR bit mask, .

#define PHYCR_LPBK

NIC_PHYCR bit mask, .

#define PHYCR_MII_DIS

NIC_PHYCR bit mask, .

#define PHYCR_PDN

NIC_PHYCR bit mask, .

#define PHYCR_RST

NIC_PHYCR bit mask, resets PHY.

#define PHYCR_SPEED

NIC_PHYCR bit mask, .

#define PHYMSK_MCWRD

NIC_PHYMSK bit mask, enables PHYSOR_CWRD interrupt.

#define PHYMSK_MDPLDT

NIC_PHYMSK bit mask, enables PHYSOR_DPLXDET interrupt.

#define PHYMSK_MESD

NIC_PHYMSK bit mask, enables PHYSOR_ESD interrupt.

#define PHYMSK_MINT

NIC_PHYMSK bit mask, enables PHYSOR_INT interrupt.

#define PHYMSK_MJAB

NIC_PHYMSK bit mask, enables PHYSOR_JAB interrupt.

#define PHYMSK_MLNKFAIL

NIC_PHYMSK bit mask, enables PHYSOR_LNKFAIL interrupt.

#define PHYMSK_MLOSSSYN

NIC_PHYMSK bit mask, enables PHYSOR_LOSSSYNC interrupt.

#define PHYMSK_MRPOL

NIC_PHYMSK bit mask, enables PHYSOR_RPOL interrupt.

#define PHYMSK_MSPDDT

NIC_PHYMSK bit mask, enables PHYSOR_SPDDET interrupt.

#define PHYMSK_MSSD

NIC_PHYMSK bit mask, enables PHYSOR_SSD interrupt.

#define PHYSOR_CWRD

NIC_PHYSOR bit mask, code word error detected.

#define PHYSOR_DPLXDET

NIC_PHYSOR bit mask, duplex detected.

#define PHYSOR_ESD

NIC_PHYSOR bit mask, end of stream error detected.

#define PHYSOR_INT

NIC_PHYSOR bit mask, interrupt bits changed.

#define PHYSOR_JAB

NIC_PHYSOR bit mask, jabber detected.

#define PHYSOR_LNKFAIL

NIC_PHYSOR bit mask, link failure detected.

#define PHYSOR_LOSSSYNC

NIC_PHYSOR bit mask, descrambler sync lost detected.

#define PHYSOR_RPOL

NIC_PHYSOR bit mask, reverse polarity detected.

#define PHYSOR_SPDDET

NIC_PHYSOR bit mask, 100/10 speed detected.

#define PHYSOR_SSD

NIC_PHYSOR bit mask, start of stream error detected.

#define PHYSR_ANEG_ACK

NIC_PHYSR bit mask, auto-negotiation completed.

#define PHYSR_CAP_ANEG

NIC_PHYSR bit mask, indicates auto-negotiation capability.

#define PHYSR_CAP_SUPR

NIC_PHYSR bit mask, indicates preamble suppression capability.

#define PHYSR_CAP_T4

NIC_PHYSR bit mask, indicates 100BASE-T4 capability.

#define PHYSR_CAP_TF

NIC_PHYSR bit mask, indicates 10BASE-T full duplex capability.

#define PHYSR_CAP_TH

NIC_PHYSR bit mask, indicates 10BASE-T half duplex capability.

#define PHYSR_CAP_TXF

NIC_PHYSR bit mask, indicates 100BASE-TX full duplex capability.

#define PHYSR_CAP_TXH

NIC_PHYSR bit mask, indicates 100BASE-TX half duplex capability.

#define PHYSR_EXREG

NIC_PHYSR bit mask, extended capabilities available.

#define PHYSR_JAB

NIC_PHYSR bit mask, jabber collision detected.

#define PHYSR_LINK

NIC_PHYSR bit mask, valid link status.

#define PHYSR_REM_FLT

NIC_PHYSR bit mask, remote fault detected.

#define RCR_ABORT_ENB

NIC_RCR bit mask, enables receive abort on collision.

#define RCR_ALMUL

NIC_RCR bit mask, multicast frames accepted when set.

#define RCR_FILT_CAR

NIC_RCR bit mask, enables carrier filter.

#define RCR_PRMS

NIC_RCR bit mask, enables promiscuous mode.

#define RCR_RX_ABORT

NIC_RCR bit mask, set when receive was aborted.

#define RCR_RXEN

NIC_RCR bit mask, enables receiver.

#define RCR_SOFT_RST

NIC_RCR bit mask, activates software reset.

#define RCR_STRIP_CRC

NIC_RCR bit mask, strips CRC.

#define RPCR_ANEG

NIC_RPCR bit mask, sets PHY in auto-negotiation mode.

#define RPCR_DPLX

NIC_RPCR bit mask, PHY operates at full duplex mode.

#define RPCR_LEDA_PAT

NIC_RPCR bit mask for LEDA mode.

#define RPCR_LEDB_PAT

NIC_RPCR bit mask for LEDB mode.

#define RPCR_SPEED

NIC_RPCR bit mask, PHY operates at 100 Mbps.

#define TCR_EPH_LOOP

NIC_TCR bit mask, enables internal loopback.

#define TCR_FDUPLX

NIC_TCR bit mask, enables receiving own frames.

#define TCR_FORCOL

NIC_TCR bit mask, forces collision.

#define TCR_LOOP

NIC_TCR bit mask, enables PHY loopback.

#define TCR_MON_CSN

NIC_TCR bit mask, enables carrier monitoring.

#define TCR_NOCRC

NIC_TCR bit mask, disables CRC transmission.

#define TCR_PAD_EN

NIC_TCR bit mask, enables automatic padding.

#define TCR_STP_SQET

NIC_TCR bit mask, enables transmission stop on SQET error.

#define TCR_SWFDUP

NIC_TCR bit mask, enables full duplex.

#define TCR_TXENA

NIC_TCR bit mask, enables transmitter.

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Typedef Documentation

typedef struct _NICINFO NICINFO

Network interface controller information type.

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