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XgNutArchArmAt91Pmc


System Clock Enable, Disable and Status Register

#define PMC_SCER_OFF   0x00000000
 System clock enable register offset.
#define PMC_SCER   (PMC_BASE + PMC_SCER_OFF)
 System clock enable register address.
#define PMC_SCDR_OFF   0x00000004
 System clock disable register offset.
#define PMC_SCDR   (PMC_BASE + PMC_SCDR_OFF)
 System clock disable register address.
#define PMC_SCSR_OFF   0x00000008
 System clock status register offset.
#define PMC_SCSR   (PMC_BASE + PMC_SCSR_OFF)
 System clock status register address.
#define PMC_PCK   0x00000001
 Processor clock.
#define PMC_UHP   0x00000040
 USB host port clock.
#define PMC_UDP   0x00000080
 USB device port clock.
#define PMC_PCK0   0x00000100
 Programmable clock 0 output.
#define PMC_PCK1   0x00000200
 Programmable clock 1 output.
#define PMC_PCK2   0x00000400
 Programmable clock 2 output.
#define PMC_PCK3   0x00000800
 Programmable clock 3 output.

Peripheral Clock Enable, Disable and Status Register

#define PMC_PCER_OFF   0x00000010
 Peripheral clock enable register offset.
#define PMC_PCER   (PMC_BASE + PMC_PCER_OFF)
 Peripheral clock enable register address.
#define PMC_PCDR_OFF   0x00000014
 Peripheral clock disable register offset.
#define PMC_PCDR   (PMC_BASE + PMC_PCDR_OFF)
 Peripheral clock disable register address.
#define PMC_PCSR_OFF   0x00000018
 Peripheral clock status register offset.
#define PMC_PCSR   (PMC_BASE + PMC_PCSR_OFF)
 Peripheral clock status register address.

Clock Generator Main Oscillator Register

#define CKGR_MOR_OFF   0x00000020
 Main oscillator register offset.
#define CKGR_MOR   (PMC_BASE + CKGR_MOR_OFF)
 Main oscillator register address.
#define CKGR_MOSCEN   0x00000001
 Main oscillator enable.
#define CKGR_OSCBYPASS   0x00000002
 Main oscillator bypass.
#define CKGR_OSCOUNT   0x0000FF00
 Main oscillator start-up time mask.
#define CKGR_OSCOUNT_LSB   8
 Main oscillator start-up time LSB.

Clock Generator Main Clock Frequency Register

#define CKGR_MCFR_OFF   0x00000024
 Main clock frequency register offset.
#define CKGR_MCFR   (PMC_BASE + CKGR_MCFR_OFF)
 Main clock frequency register address.
#define CKGR_MAINF   0x0000FFFF
 Main clock frequency mask mask.
#define CKGR_MAINF_OFF   0
 Main clock frequency mask LSB.
#define CKGR_MAINRDY   0x00010000
 Main clock ready.

PLL Registers

#define CKGR_DIV   0x000000FF
 Divider.
#define CKGR_DIV_LSB   0
 Least significant bit of the divider.
#define CKGR_DIV_0   0x00000000
 Divider output is 0.
#define CKGR_DIV_BYPASS   0x00000001
 Divider is bypassed.
#define CKGR_PLLCOUNT   0x00003F00
 PLL counter mask.
#define CKGR_PLLCOUNT_LSB   8
 PLL counter LSB.
#define CKGR_OUT   0x0000C000
 PLL output frequency range.
#define CKGR_OUT_0   0x00000000
 Please refer to the PLL datasheet.
#define CKGR_OUT_1   0x00004000
 Please refer to the PLL datasheet.
#define CKGR_OUT_2   0x00008000
 Please refer to the PLL datasheet.
#define CKGR_OUT_3   0x0000C000
 Please refer to the PLL datasheet.
#define CKGR_MUL   0x07FF0000
 PLL multiplier.
#define CKGR_MUL_LSB   16
 Least significant bit of the PLL multiplier.
#define CKGR_USBDIV   0x30000000
 Divider for USB clocks.
#define CKGR_USBDIV_1   0x00000000
 Divider output is PLL clock output.
#define CKGR_USBDIV_2   0x10000000
 Divider output is PLL clock output divided by 2.
#define CKGR_USBDIV_4   0x20000000
 Divider output is PLL clock output divided by 4.

Master Clock Register

#define PMC_MCKR_OFF   0x00000030
 Master clock register offset.
#define PMC_MCKR   (PMC_BASE + PMC_MCKR_OFF)
 Master clock register address.
#define PMC_ACKR_OFF   0x00000034
 Application clock register offset.
#define PMC_ACKR   (PMC_BASE + PMC_ACKR_OFF)
 Application clock register address.
#define PMC_PCKR0_OFF   0x00000040
 Programmable clock 0 register offset.
#define PMC_PCKR0   (PMC_BASE + PMC_PCKR0_OFF)
 Programmable clock 0 register address.
#define PMC_PCKR1_OFF   0x00000044
 Programmable clock 1 register offset.
#define PMC_PCKR1   (PMC_BASE + PMC_PCKR1_OFF)
 Programmable clock 1 register address.
#define PMC_PCKR2_OFF   0x00000048
 Programmable clock 2 register offset.
#define PMC_PCKR2   (PMC_BASE + PMC_PCKR2_OFF)
 Programmable clock 2 register address.
#define PMC_PCKR3_OFF   0x0000004C
 Programmable clock 3 register offset.
#define PMC_PCKR3   (PMC_BASE + PMC_PCKR3_OFF)
 Programmable clock 3 register address.
#define PMC_CSS   0x00000003
 Clock selection mask.
#define PMC_CSS_SLOW_CLK   0x00000000
 Slow clock selected.
#define PMC_CSS_MAIN_CLK   0x00000001
 Main clock selected.
#define PMC_PRES   0x0000001C
 Clock prescaler mask.
#define PMC_PRES_LSB   2
 Clock prescaler LSB.
#define PMC_PRES_CLK   0x00000000
 Selected clock, not divided.
#define PMC_PRES_CLK_2   0x00000004
 Selected clock divided by 2.
#define PMC_PRES_CLK_4   0x00000008
 Selected clock divided by 4.
#define PMC_PRES_CLK_8   0x0000000C
 Selected clock divided by 8.
#define PMC_PRES_CLK_16   0x00000010
 Selected clock divided by 16.
#define PMC_PRES_CLK_32   0x00000014
 Selected clock divided by 32.
#define PMC_PRES_CLK_64   0x00000018
 Selected clock divided by 64.

Power Management Status and Interrupt Registers

#define PMC_IER_OFF   0x00000060
 Interrupt enable register offset.
#define PMC_IER   (PMC_BASE + PMC_IER_OFF)
 Interrupt enable register address.
#define PMC_IDR_OFF   0x00000064
 Interrupt disable register offset.
#define PMC_IDR   (PMC_BASE + PMC_IDR_OFF)
 Interrupt disable register address.
#define PMC_SR_OFF   0x00000068
 Status register offset.
#define PMC_SR   (PMC_BASE + PMC_SR_OFF)
 Status register address.
#define PMC_IMR_OFF   0x0000006C
 Interrupt mask register offset.
#define PMC_IMR   (PMC_BASE + PMC_IMR_OFF)
 Interrupt mask register address.
#define PMC_MOSCS   0x00000001
 Main oscillator.
#define PMC_MCKRDY   0x00000008
 Master clock ready.
#define PMC_OSC_SEL   0x00000080
 Slow clock oscillator selection.
#define PMC_PCKRDY0   0x00000100
 Programmable clock 0 ready.
#define PMC_PCKRDY1   0x00000200
 Programmable clock 1 ready.
#define PMC_PCKRDY2   0x00000400
 Programmable clock 2 ready.
#define PMC_PCKRDY3   0x00000800
 Programmable clock 3 ready.


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