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Peripheral Identifiers and Interrupts |
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#define | FIQ_ID 0 |
| | Fast interrupt ID.
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#define | SWIRQ_ID 1 |
| | Software interrupt ID.
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#define | US0_ID 2 |
| | USART 0 ID.
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#define | US1_ID 3 |
| | USART 1 ID.
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#define | TC0_ID 4 |
| | Timer 0 ID.
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#define | TC1_ID 5 |
| | Timer 1 ID.
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#define | TC2_ID 6 |
| | Timer 2 ID.
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#define | WDI_ID 7 |
| | Watchdog interrupt ID.
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#define | PIO_ID 8 |
| | Parallel I/O controller ID.
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#define | IRQ0_ID 16 |
| | External interrupt 0 ID.
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#define | IRQ1_ID 17 |
| | External interrupt 1 ID.
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#define | IRQ2_ID 18 |
| | External interrupt 2 ID.
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Defines |
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#define | EBI_BASE 0xFFE00000 |
| | EBI base address.
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#define | SF_BASE 0xFFF00000 |
| | Special function register base address.
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#define | USART1_BASE 0xFFFCC000 |
| | USART 1 base address.
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#define | USART0_BASE 0xFFFD0000 |
| | USART 0 base address.
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#define | TC_BASE 0xFFFE0000 |
| | TC base address.
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#define | PIO_BASE 0xFFFF0000 |
| | PIO base address.
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#define | PS_BASE 0xFFFF4000 |
| | PS base address.
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#define | WD_BASE 0xFFFF8000 |
| | Watch Dog register base address.
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| #define | AIC_BASE 0xFFFFF000 |
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#define | PERIPH_RPR_OFF 0x00000030 |
| | Receive pointer register offset.
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#define | PERIPH_RCR_OFF 0x00000034 |
| | Receive counter register offset.
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#define | PERIPH_TPR_OFF 0x00000038 |
| | Transmit pointer register offset.
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#define | PERIPH_TCR_OFF 0x0000003C |
| | Transmit counter register offset.
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#define | USART_HAS_PDC |